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Causa cur directe in riscv-archi-test focus est, quia RISCOF test compage utitur riscv-archi-test.

1. De architecturae test

Test architecturae una probatio est quae minimum codicem testium exhibet qui componi et currere potest. Legitur in codice comitiali eiusque producto subscriptio nota est. Examen architecturae multiplicibus casibus experimentis constare potest.

2. De RISC-V test architecturae piscinae

RISC-V probatio architecturae piscinae constat ex omnibus probatis architecturae probationibus quae a test compage in testem architecturae suite componi possunt. RISC-V examinis architecturae bibliothecae scopo agnostico probare debent (et ideo recte in quolibet scopo faciliori currere debent). Quaeso nota hanc probationem non-muneris non substitui probationis seu fabricae probationis.

2.1 Test stagnum compages

architectural-tests-suite (root)
|-- <architecture>_<mode>/<feature(s)>, where
<architecture> is [ RV32I | RV64I | RV32E ]
<mode> is [ M | MU | MS | MSU ], where
   M   Machine      mode tests - tests execute in M-mode only
   MU  Machine/User mode tests - tests execute in both M- & U-modes (S-mode may exist)
   MS  Machine/Supv mode tests - tests execute in both M- & S-modes (not U-mode)
   MSU All          mode tests - tests execute in all of M-, S-, & U-Modes
<feature(s)> are the lettered extension [A | B | C | M ...] or subextension [Zifencei | Zam | ...] when the tests involve extensions, or more general names when tests cut across extension definitionss (e.g. Priv, Interrupt, Vm). The feature string consists of an initial capital letter, followed by any further letters in lower case.
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Machina Modus Processus Instructionis pone Characteres Register (MISA)
misa = 0x800000000094112f
Repraesentatio binarii: 1000000000000000000000000000000000000001001010000001000100101111

riscv-arcus-test/riscv-test-suite$ ls
env/ Makefile.include README.md rv32e_m/ rv32i_m/ rv64i_m/
riscv-arcus-test/riscv-test-suite/rv64i_m$ ls
A/B/C/CMO/D/F/I/K/M/PRIVILEGIUM/P_unratified/ Zfh/Zfinx/Zicond/Zifencei/

3. De RISC-V test architecturae suite

RISC-V testium architecturae synthesis est certa testium e piscina testium architecturae selectarum ad probandum conformitatem cuiusdam RISC-V configurationis. Proventus testium in forma testium subscriptionis suite obtinentur. Test lectio innititur in scopum asserti configurationis, specificationis, executionis ambitus, seu suggesti requisita. Facilis processus seu processus exemplar debet idem Aurum Reference Test Suite subscriptio ut certae figurae probatio ostendat.

4. In test causa

Causae testium partem sunt probandi architecturae et probandi unam tantum functionem specificationis.
Nota: Expertus plures casus testium continere potest, et unaquaeque causa testium condiciones inclusionis habet (per modum cond_str parametri RVTEST_CASE tortor definitur).

4.1 Test nominatio

<test objective>-<test number>.S
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riscv-arcus-test/riscv-test-suite/rv64i_m/I/src$ls
add-01.S and-01.S bge-01.S bne-01.S lb-align-01.S lhu-align-01.S misalign1-jalr-01.S sd-align-01.S slliw- 01.S sltiu-01.S sraiw-01.S srliw-01.S sw-align-01.S
addi-01.S andi-01.S bgeu-01.S sepe-01.S lbu-align-01.S lui-01.S or-01.S sh-align-01.S sllw-01.S sltu -01.S sraw-01.S srlw-01.S xor-01.S
addiw-01.S auipc-01.S blt-01.S jal-01.S ld-align-01.S lw-align-01.S ori-01.S sll-01.S slt-01.S sra -01.S srl-01.S sub-01.S xori-01.S
addw-01.S beq-01.S bltu-01.S jalr-01.S lh-align-01.S lwu-align-01.S sb-align-01.S slli-01.S slti-01. S srai-01.S srli-01.S subw-01.S

5. Conventus Testium infrastructure (ac exemplum accipe ./rv32i_m/I/src/add-01.S)

//
// This assembly file tests the add instruction of the RISC-V I extension for the add covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add)

RVTEST_SIGBASE( x3,signature_x3_1)

inst_0:
// rs2 == rd != rs1, rs1==x4, rs2==x24, rd==x24, rs1_val > 0 and rs2_val > 0, rs2_val == 1, rs1_val == (2**(xlen-1)-1), rs1_val != rs2_val, rs1_val == 2147483647
// opcode: add ; op1:x4; op2:x24; dest:x24; op1val:0x7fffffff;  op2val:0x1
TEST_RR_OP(add, x24, x4, x24, 0x80000000, 0x7fffffff, 0x1, x3, 0, x18)

inst_1:
// rs1 == rs2 != rd, rs1==x10, rs2==x10, rd==x28, rs1_val > 0 and rs2_val < 0, rs2_val == -257, rs1_val == 131072
// opcode: add ; op1:x10; op2:x10; dest:x28; op1val:0x20000;  op2val:0x20000
TEST_RR_OP(add, x28, x10, x10, 0x40000, 0x20000, 0x20000, x3, 4, x18)

inst_2:
// rs1 == rs2 == rd, rs1==x21, rs2==x21, rd==x21, rs1_val < 0 and rs2_val < 0, rs1_val == -16777217
// opcode: add ; op1:x21; op2:x21; dest:x21; op1val:-0x1000001;  op2val:-0x1000001
TEST_RR_OP(add, x21, x21, x21, 0xfdfffffe, -0x1000001, -0x1000001, x3, 8, x18)
......
......
......
RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4

rvtest_data:
.word 0xbabecafe
.word 0xbabecafe
.word 0xbabecafe
.word 0xbabecafe
RVTEST_DATA_END

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;

signature_x3_0:
    .fill 0*(XLEN/32),4,0xdeadbeef

signature_x3_1:
    .fill 17*(XLEN/32),4,0xdeadbeef

signature_x8_0:
    .fill 16*(XLEN/32),4,0xdeadbeef

signature_x1_0:
    .fill 512*(XLEN/32),4,0xdeadbeef

signature_x1_1:
    .fill 43*(XLEN/32),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*(XLEN/32),4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
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Brevis expositio codicis suprascripti conventus haec est:

1. Header ad inlcude comment

#Haec fasciculus conventus documentum probat additamentum institutionis RISC-V I extensionis pro adigendo coetus.

2. Includes header files

#include "model_test.h"
#include "arch_test.h"

Singulae testi nonnisi sequentes fasciculi caput includere debent:
model_test.h - scopum specialium macros definit, inter quas requiritur et ad libitum macros: (exampla RVMODEL_xxx)
arch_test.h - praedefinitas test macros definit, inter requiri utris et macros libitum: (ut RVTEST_xxx)

3. TVM constitue de test

RVTEST_ISA("RV32I")

4. Test scopum specifica tabernus, codice

RVMODEL_BOOT

5. Ad initium GPR initialization exercitatione ac test codice

RVTEST_CODE_BEGIN

6. Definire RVTEST_CASE filum et condiciones

#ifdef TEST_CASE_1
// Haec probatio ad rv32I extensionem machinarum exsequendam destinatur et ut compilationem requirit
// tortor TEST_CASE_1. Hic testis conferet ad pittacium "addendi" coverage.
RVTEST_CASE(0,"//reprehendo ISA:=regex(.32.) Isaiah reprehendo: = regex (.EGO.);def TEST_CASE_1 = Verum;", add)

7. Initialize regula signature regionem

RVTEST_SIGBASE(x16,signature_x16_1) // x16 designabit pittacium signature_x16_1 in actis regionis

8. Test casibus definias

inst_0:
// rs2 == rd != rs1, rs1==x4, rs2==x24, rd==x24, rs1_val > 0 and rs2_val > 0, rs2_val == 1, rs1_val == (2**(xlen-1)-1), rs1_val != rs2_val, rs1_val == 2147483647
// opcode: add ; op1:x4; op2:x24; dest:x24; op1val:0x7fffffff;  op2val:0x1
TEST_RR_OP(add, x24, x4, x24, 0x80000000, 0x7fffffff, 0x1, x3, 0, x18)

inst_1:
// rs1 == rs2 != rd, rs1==x10, rs2==x10, rd==x28, rs1_val > 0 and rs2_val < 0, rs2_val == -257, rs1_val == 131072
// opcode: add ; op1:x10; op2:x10; dest:x28; op1val:0x20000;  op2val:0x20000
TEST_RR_OP(add, x28, x10, x10, 0x40000, 0x20000, 0x20000, x3, 4, x18)
...
...
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//Tests for a instructions with register-register operand
#define TEST_RR_OP(inst, destreg, reg1, reg2, correctval, val1, val2, swreg, offset, testreg) 
    TEST_CASE(testreg, destreg, correctval, swreg, offset, 
      LI(reg1, MASK_XLEN(val1))                        ;
      LI(reg2, MASK_XLEN(val2))                        ;
      inst destreg, reg1, reg2                        ;
    )
#define TEST_CASE(testreg, destreg, correctval, swreg, offset, code... )        ;
    code                                ;
    RVTEST_SIGUPD(swreg,destreg,offset)        ;
    RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval)

 /* automatically adjust base and offset if offset gets too big, resetting offset                                 */
 /* RVTEST_SIGUPD(basereg, sigreg)          stores sigreg at offset(basereg) and updates offset by regwidth         */
 /* RVTEST_SIGUPD(basereg, sigreg,newoff) stores sigreg at newoff(basereg) and updates offset to regwidth+newoff */
#define RVTEST_SIGUPD(_BR,_R,...)                        ;
  .if NARG(__VA_ARGS__) == 1                                ;
        .set offset,_ARG1(__VA_OPT__(__VA_ARGS__,0))        ;
  .endif                                                ;
  CHK_OFFSET(_BR, REGWIDTH,0)                                ;
  SREG _R,offset(_BR)                                        ;
  .set offset,offset+REGWIDTH
  
  RVMODEL_IO_ASSERT_GPR_EQ 定义在target的model_test.h中```

在咱们得model_test.h中将RVMODEL_IO_ASSERT_GPR_EQ 宏定义如下：比较错误的话，往0xF0000080写1

```c
#define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I)  
    li _S, 0xF0000080;         
    mv t0, _R;                 
    li t3, _I;                 
    beq t0, t3, 1f;            
    li t2, 1;                  
    sw t2, 0(_S);              
    j 2f;                      
1:                             
    li t2, 0;                  
    sw t2, 0(_S);              
2:                             
    nop;```

在tb.v中加入监测对AXI 写地址总线，地址0xF0000080的监测，如果出现fail_cnt >0，可以判断该testcase错误

```c
// RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval) used to check destreg == correctval
// destreg != correctva write testreg 1, else write testreg 0
always @(posedge `CPU_CLK) begin
    if ((cpu_awaddr[31:0] == 32'hF000_0080) && cpu_wvalid && `clk_en && (cpu_wstrb[15:0] == 16'hf)) begin
       if(`SOC_TOP.biu_pad_wdata == 1'b1) begin
         fail_cnt ++;
       end
    end
end
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9. Mutatio signature basis mandare

// this will change the signature base register to x3. x3 will not point to signature_x3_0 in
// the signature region
RVTEST_SIGBASE( x3,signature_x3_0)

// continue with new test cases ..
TEST_RR_OP(add, x4, x24, x27, 0x55555955, 0x00000400, 0x55555555, x3, 0, x5)
...
...
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10. Finire test et consistere in test-scopum

RVTEST_CODE_END
RVMODEL_HALT
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11. Create test initus notitia sectionem

RVTEST_DATA_BEGIN
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END
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12. Create pre-onusta regione signature

RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;

signature_x3_0:
    .fill 0*(XLEN/32),4,0xdeadbeef

signature_x3_1:
    .fill 17*(XLEN/32),4,0xdeadbeef

signature_x8_0:
    .fill 16*(XLEN/32),4,0xdeadbeef

signature_x1_0:
    .fill 512*(XLEN/32),4,0xdeadbeef

signature_x1_1:
    .fill 43*(XLEN/32),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

tsig_begin_canary:
CANARY;
mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*(XLEN/32),4,0xdeadbeef

#endif

sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END
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RA6 Ad sextum test causa signature

Subscriptio casus probatus repraesentatur per valores singulares vel plures. Valor scribetur in memoriam ab inscriptione ab RVMODEL_DATA_BEGIN specificata et in inscriptione ab RVMODEL_DATA_END terminata. Signaturae facile generantur utens tortor RVTEST_SIGUPD.

RA7 Ad septimum dicendum test signature

Subscriptio probata est proprietas pretii quae ex experimento architecturae generatur. Subscriptio probata constare potest ex pluribus testi- moniis subscriptionibus, praefixa linea separata continens nomen testi et singularem valorem eius versionem indicans. Scopum probatum est responsabilis ad extrahendos valores ex memoria et formando eas convenienter, utens metadata in compage, utens RVMODEL_DATA_BEGIN et RVMODEL_DATA_END macros.Subscriptio casus probatus valor in versibus scriptus est, incipiens a insignium byte in sinistra, in forma<hex_value> , ubi longitudo valoris erit 32 frusta (sic 8 characters), dum calculus actualis testium longitudinem valoris rationem non accipit. Documenta condita debent esse a valore in infima inscriptionis subscriptionis (hoc est, a RVMODEL_DATA_BEGIN ad RVMODEL_DATA_END). Accedit, subscriptio semper in 16-byte (128-bit) incipere debet, et magnitudo subscriptionis multiplex 4 bytes esse debet (id est, etiam in 4-byte terminus finire debet).

8. test signature suite

Subscriptio suiti testium definitur ut certa subscriptionum testium quae validae sunt pro asse testudinis architecturae. Testam subscriptionem repraesentat syngraphae testium architecturae selectae pro certa configuratione RISC-V.

9. RISCOF probatio compage

RISCOF - The RISC-V Compatibilitas Framework est Python-substructio compage quae dat usum testium architecturae RISC-V statuti risc-V tentandi scuta (exsecutiones hardware vel software) ad convenientiam cum norma RISC-V aureae Reference Exemplar sexus.

RISC-V Configurationis Validator : RISCV-Mando
RISC-V Compliance Test Generator : RISC-V CTG
RISC-V ISA Coverage : RISC-V ISAC
Ut in RISCOF ut normaliter percurrat probationem, sequentia contenta praebenda sunt:

• config.ini: Hic fasciculus lima fundamentalis conformatio et ini syntaxis sequitur. Haec fasciculus informationes capiet ut: nomen DUT/reference plugin, semita ad plugin, semita ad YAML fasciculi in riscv-mando, etc.
• directorium dut-plugin: RISCOF requirit ut exemplar probatum DUT in obturaculum Pythonis forma praebeatur. Python obturaculum in actu est fasciculus Python, qui continet quasdam regulas et definitas functiones ad faciendum testium compilationem, executionem, et subscriptio extractionis operationis. Nomen fasciculi huius Pythonis cum riscof_ praefixo esse debet et in presul dut-plugin esse debet. Pythone obturaculum in sectione fasciculi referre potes ut scias quomodo hoc Python lima scribam.
  Hoc indicis etiam opus est ad limam isa et suggestum YAML in riscv-mando continere, quae definitionem DUT praebent. Haec YAML fasciculi adhibebuntur ad eliquare probationes quae in Diff currere debent.
  Denique env directorium necesse est esse in directorio dut-plugin, quod in ambitu imagini continetur, sicut exemplar_test.h, quae ad probationes componendas et currendum requiruntur. Placere referri ad specificationem TestFormat pro definitionibus macros quae in tabella exemplar_test.h adhiberi possunt. In env directorio etiam alias tabulas continere potest, ut scriptorum nexus et scriptorum post-processus ut users egere possint.
• reference-plugin directorium: Similia cum obturaculum in DUT, RISCOF etiam requirit exemplar obturaculum-in referentia. Directorium et lima structura eadem est ac Diff. Sed isa et suggestum YAML lima non requiritur quod RISCOF limas YAML semper eligere ad omnes usus e obturaculum-in DUT.
  Ut operationem simpliciorem reddant, RISCOF vexillum DUT gignit et exemplar exempla praeset referentia pro usoribus ordinandis praecipiens, ut in sequenti figura ostenditur:

$ riscof setup --dutname=spike

Praeceptum mandatum sequentes tabulas et directoria in directorio currenti generabit:

config.ini # configuration file pro riscof
spic/#DUT plugin template
env
link.ld #DUT linker scriptor
model_test.h # DUT specifica header file
riscof_spike.py # DUT python plugin
spike_isa.yaml # DUT ISA yaml fundatur in riscv-mando
spike_platform.yaml # DUT Platform yaml fundatur in riscv-mando
sail_cSim/ # referat plugin templates
env
link.ld # Relatio linker scriptor
model_test.h # Reference model specifica header file
├── in illud.py
riscof_sail_cSim.py # Reference exemplar python plugin.

Iustus supra clavum ad C920 plugin muto. Utique, debes singula limam configurationem et fasciculum pythonis mutare.
c920_isa.yaml

hart_ids: [0]
hart0:
  ISA: RV64IMAFDCVZicsr_Zicbom_Zicbop_Zicboz_Zihintpause_Zfh_Zca_Zcb_Zcd_Zba_Zbb_Zbc_Zbs
  physical_addr_sz: 40
  User_Spec_Version: "2.2"
  Privilege_Spec_Version: "1.10"
  hw_data_misaligned_support: false
  pmp_granularity: 4
  supported_xlen: [64]
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c920_platform.yaml

mtime:
  implemented: true
  address: 0xBFF8
mtimecmp:
  implemented: true
  address: 0x4000
nmi:
  label: nmi_vector
reset:
  address: 0x000000000 
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Exsequens mandatum sequens album casus extrahet e test_list.yaml et discurret utrobique.

riscof run --config=config.ini
-suite=riscv-arch-test/riscv-test-suite/
-env=riscv-arch-test/riscv-test-suite/env
-testfile=riscof_work/test_list.yaml

Mandatum hoc exequens test_list.yaml generabit et regressionem currunt

riscof run --config=config.ini
-suite=riscv-arch-test/riscv-test-suite/
-env=riscv-arch-test/riscv-test-suite/env

Test eventus 10.

Error causa analysis:
Primus:

Est quod per compilationem error offendit

    INFO | Compiling test: /ssd_fes/jiongz/desktop/github/c920_riscof1/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/beq-01.S
   ERROR | /opt/picocom/ThirdParty_Libs/T-head/C920_R2S0P21/C920_R2S0_manuals_and_tools/manuals_and_tools/08_toolchain_900_series_cpu_toolchain/V2.8.0/Xuantie-900-gcc-elf-newlib-x86_64-V2.8.0/bin/../lib/gcc/riscv64-unknown-elf/10.4.0/../../../../riscv64-unknown-elf/bin/ld: main.elf section `.text' will not fit in region `MEM1'
collect2: error: ld returned 1 exit status
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Secundum genus;

Id est c920 certum mandatum per defaltam non dat.

11. rv64i_m/I/src/add-01.S waveform

Est etiam tortor in model_test.h pro TUBER subscriptione et simulatione consummationis

// This will dump the test results (signature) via the testbench dump module.
#define RVMODEL_HALT                                          
    signature_dump:                                           
      la   a0, begin_signature;                               
      la   a1, end_signature;                                 
      li   a2, 0xF0000040;                                    
    signature_dump_loop:                                      
      bge  a0, a1, signature_dump_end;                        
      lw   t0, 0(a0);                                         
      sw   t0, 0(a2);                                         
      addi a0, a0, 4;                                         
      j    signature_dump_loop;                               
    signature_dump_end:                                       
      nop;                                                    
    terminate_simulation:                                     
      li   a0, 0xF0000000;                                    
      li   a1, 0xCAFECAFE;                                    
      sw   a1, 0(a0);                                         
      j    terminate_simulation
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Respondentem tb.v*

always @(posedge `CPU_CLK or negedge `CPU_RST) begin
    if (!`CPU_RST) begin
        msi <= 1'b0;
        mei <= 1'b0;
        mti <= 1'b0;
    end else begin
        //if ((wb_cpu.cyc == 1'b1) && (wb_cpu.stb == 1'b1) && (wb_cpu.we == 1'b1) && (cpu_awaddr[31:0] == 32'hF000_0000)) begin
        if ((cpu_awaddr[31:0] == 32'hF000_0000) && cpu_wvalid && `clk_en && (cpu_wstrb[15:0] == 16'hf)) begin
            case (`SOC_TOP.biu_pad_wdata[31:0])
                32'hCAFE_CAFE: begin // end simulation
                    $display("Finishing simulation.");
                    #100;
                    if(fail_cnt >0) begin
                     $error("This case test failed!");
                    end
                    $finish;
                end
                ......
 end

// Signature Dump
int dump_file; // Declare file handle
always @(posedge `CPU_CLK) begin
    if ((cpu_awaddr[31:0] == 32'hF000_0040) && cpu_wvalid && `clk_en && (cpu_wstrb[15:0] == 16'hf)) begin
        if (!dump_file) begin // Check if file is already open
            dump_file = $fopen("DUT-c920.signature", "w"); // Open file if not already opened
        end
        //for (int i = 7; i >= 0; i--) begin
        //    $fwrite(dump_file, "%hn", `SOC_TOP.biu_pad_wdata[i*4 +: 4]); // Write data
        //end
        $fwrite(dump_file, "%hn", `SOC_TOP.biu_pad_wdata[31:0]); // Write data
    end
    else if((cpu_awaddr[31:0] == 32'hF000_0000) && cpu_wvalid && `clk_en && (cpu_wstrb[15:0] == 16'hf)) begin
        if (dump_file) begin // If file is open, close it
            $fclose(dump_file);
            dump_file = 0; // Reset file handle to 0 indicating file is closed
        end
    end
end

// RVMODEL_IO_ASSERT_GPR_EQ(testreg, destreg, correctval) used to check destreg == correctval
// destreg != correctva write testreg 1, else write testreg 0
always @(posedge `CPU_CLK) begin
    if ((cpu_awaddr[31:0] == 32'hF000_0080) && cpu_wvalid && `clk_en && (cpu_wstrb[15:0] == 16'hf)) begin
       if(`SOC_TOP.biu_pad_wdata == 1'b1) begin
         fail_cnt ++;
       end
    end
end
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#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64I")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add)

RVTEST_SIGBASE( x8,signature_x8_1)

inst_0:
// rs1 == rs2 != rd, rs1==x0, rs2==x0, rd==x20, rs1_val > 0 and rs2_val > 0, rs1_val == 4, rs1_val==4 and rs2_val==6148914691236517206, rs1_val != rs2_val
// opcode: add ; op1:x0; op2:x0; dest:x20; op1val:0x0;  op2val:0x0
TEST_RR_OP(add, x20, x0, x0, 0x0, 0x0, 0x0, x8, 0, x16)

inst_1:
// rs2 == rd != rs1, rs1==x2, rs2==x26, rd==x26, rs1_val > 0 and rs2_val < 0, rs2_val == -1073741825
// opcode: add ; op1:x2; op2:x26; dest:x26; op1val:0x5;  op2val:-0x40000001
TEST_RR_OP(add, x26, x2, x26, 0xffffffffc0000004, 0x5, -0x40000001, x8, 8, x16)

inst_2:
// rs1 == rs2 == rd, rs1==x22, rs2==x22, rd==x22, rs1_val < 0 and rs2_val < 0, rs1_val == -8388609
// opcode: add ; op1:x22; op2:x22; dest:x22; op1val:-0x800001;  op2val:-0x800001
TEST_RR_OP(add, x22, x22, x22, 0xfffffffffefffffe, -0x800001, -0x800001, x8, 16, x16)
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Contentum "riscof_work/rv64i_m/I/src/add-01.S/dut/DUT-c920.signature" hoc modo est:

e7d4b281
6f5ca309
00000000
00000000
c0000004
ffffffff
fefffffe
ffffffff
fffffbf
007fffff
00000080
00000000
66666665
e6666666
00000001
00000000
0001ffff
80000000
10000001
00000000
fffffeff