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please read【ARM GICv3/v4 practical learning】

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GIC various interrupt enable configuration

In the ARM GICv3 and GICv4 architectures, different types of interrupts (such as PPIs, SPIs, SGIs, and LPIs) can be enabled and disabled in different ways.


The following details how to enable and disable these interrupts:

PPIs (Private Per Processor Interrupts)

• Enabling and disabling PPIs：ThroughGICR_ISENABLER0andGICR_ICENABLER0Register writes can enable and disable PPIs in a secure state with affinity routing enabled.
  If traditional operation of physical interrupts is supported and configured, for PPIsn = 0, that is, there is only one register.GICD_ISENABLER<n>andGICD_ICENABLER<n>Write to enable and disable PPIs individually.

Traditional operating mode of physical interruptionLegacy Operation for Physical Interrupts usually refers to support for earlier ARM architectures, where interrupt management may differ from the latest GIC specifications.