Technology Sharing

한어Русский языкEnglishFrançaisIndonesianSanskrit日本語DeutschPortuguêsΕλληνικάespañolItalianoSuomalainenLatina

• Classification of digital circuits: combinational logic circuits and sequential logic circuits.
• In this chapter we study combinational logic circuits.

4.1 Analysis of Combinational Logic Circuits

• Given a logic circuit, determine its logical expression, list the truth table, obtain the simplified logical expression, and analyze it to obtain its function.

3-bit odd parity circuit

(1) As shown in the figure below.

(2) List the truth table

(3) AnalyzeOdd parity circuitFunction.

• When C is 1, and there are 0 or 2 1s in AB (AB is the same, Z=0), (an odd number of 1s), L is 1.
• When C is 0 and there is only one 1 in AB (AB is different, Z=1), (an odd number of 1s), L is 1.
• That is, when an odd number of 1s appears in ABC, L is 1. When an even number of 1s appears in ABC, L is 0.

3-bit even parity circuit

(1) Based on the odd-parity circuit, adding an inverter at the output end can obtainEven parity circuit。

3-bit inverted code circuit

• As shown below.
  
• Logical expression.
  $X=A$
  $Y=\overline{(\overline{A\cdot \overline{B}})\cdot (\overline{\overline{A}\cdot B)}}=A\cdot \overline{B}+\overline{A}\cdot B$
  $Z=\overline{(\overline{\overline{A}\cdot C})\cdot (\overline{A\cdot \overline{C})}}=\overline{A}\cdot C+A\cdot \overline{C}$
• Truth table.

• Functional Analysis.
  (1) In the original code ABC, A is the sign bit, 0 represents a positive number, and 1 represents a negative number.
  (2) The two’s complement is XYZ, where X is the sign bit, which is the same as A.
  (3) When A=0, a positive number, YZ and BC are consistent.
  (4) When A=1 is a negative number, the sign bit remains unchanged and X=A, and YZ is the result of inverting BC.

4.2 Combinational Logic Circuit Design

• Clarify logical functions, determine inputs and outputs, list truth tables, write logical expressions, simplify and transform logical expressions, and draw logic diagrams.

3-digit train arrival indicator light

• need.
  (1) Using 2 inputsNAND Gate,inverter.
  (2) Indicator light No. 1, the indicator light for express trains entering the station. It has a high priority.
  (3) Indicator light No. 2, the indicator light for express trains entering the station. Medium priority.
  (4) Indicator light No. 3, slow train approaching station indicator light. Low priority.
  (5) Only one indicator light can be on at a time.

• Define input and output variables.
  (1) Input signal,$I_{0}Express\; request,I_{1}Please\; ask\; immediately.I_{2}Slow\; train\; request$1 means there is a request to enter the station, and 0 means there is no request to enter the station.
  (2) Output signal,$L_{0}Express\; arrival\; indicator\; light,L_{1}Fast-track\; indicator\; light,L_{2}Slow\; train\; approaching\; station\; indicator$1 means the light is on, 0 means the light is off.

• Truth table.

• List logical expressions
  $L_0=I_0$
  $L_1=\overline{I_0}\cdot I_1$
  $L_2=\overline{I_0}\cdot \overline{I_1}\cdot I_2$

• Transform to the AND-NOT form as required.
  $L_0=I_0$
  $L_1=\overline{\overline{\overline{I_0}\cdot I_1}}$
  $L_2=\overline{\overline{\overline{\overline{\overline{I_0}\cdot \overline{I_1}}}\cdot I_2}}$

• Draw a logic diagram.
  (1) A 74HC00 chip, containing four 2-input CMOS NAND gates.
  (2) A 74HC04 chip contains 6 CMOS inverters.
  

4-bit Gray code to natural binary code

• need.
  (1) Any logic gate circuit can be used.
  (2) 4-bit Gray code, converted to natural binary code.

• Define input and output variables.
  (1) Input variables,$G_3,G_2,G_1,G_0$。
  (2) Output variables,$B_3,B_2,B_1,B_0$。

• List the truth table.

• Based on the truth table, draw the Karnaugh map.
  
  

• Lists logical expressions.
  $B_3=G_3$
  $B_2=\overline{G_3}\cdot G_2+G_3\cdot \overline{G_2}=G_3\oplus G_2$
  $B_1=\overline{G_3}{G}_2\overline{G_1}+G_3\overline{G_2}\overline{G_1}+\overline{G_3}\overline{G_2}{G}_1+G_3{G}_2{G}_1=(G_3\overline{G_2}+\overline{G_3}{G}_2)\overline{G_1}+\overline{(G_3\overline{G_2}+\overline{G_3}{G}_2)}{G}_1=G_3\oplus G_2\oplus G_1$
  $B_0=G_3\oplus G_2\oplus G_1\oplus G_0$

• Draw a logic diagram.
  

4.3 Competition and Risk-Taking in Combinational Logic Circuits

• In a combinational logic circuit, it takes a certain amount of time for a signal to pass through a logic gate.
• The signal takes different transmission times when it passes through different paths (different levels of logic gates and different types of logic gates).
• Competition: The phenomenon that the signals at multiple input terminals of a logic gate change in opposite directions at the same time and at different times is called "competition". (Who changes first and who changes later is the competition).
• Hazard: The output interference narrow pulses generated by competition are called hazard.

4.3.1 Reasons for competitive risk-taking

• The input signals do not arrive simultaneously, resulting in abnormally narrow pulses of short duration.
• AND Gate
  
• OR Gate
  

4.3.2 Methods to Eliminate Competitive Risk

1. Find and eliminate complementary multiplication terms

• $F=(A+B)(\overline{A}+C)$
• When B=C=0, there will be$A\overline{A}$Product term.
• Discover:$A\overline{A}$Product terms may lead to "competitive hazard".
  
• Complementary and multiplicative terms: $A\cdot \overline{A}$。
• Elimination: $F=(A+B)(\overline{A}+C)=A\overline{A}+AC+B\overline{A}+BC=AC+B\overline{A}+BC$In this way, there are no complementary items, and to a certain extent, competition and risk-taking are avoided.

2. Add product terms to avoid adding complementary terms

• As mentioned above,$F=AC+B\overline{A}+BC$, when B=C=1,$F=A+\overline{A}+1=1$The BC product term here = 1, which plays a role in avoiding the competition hazard of adding complementary terms.
• according toCommonly used identities "or" operation(Section 2.1),$AB+\overline{A}C+BC=AB+\overline{A}C$。
• When encountering a logical function$L=AC+B\overline{C}$In this form, we can add the product term$AB$。
  

3. Connect capacitor in parallel with the output

• For slower working scenarios.
• The capacitance value is 4~20pF. It plays the role of "smoothing" the dangerous narrow pulse.
• Disadvantages: It will make the rising and falling edges of the output waveform slow down.

4.4 (Learning Focus) Some Typical Combinational Logic Integrated Circuits

• Encoder, decoder, data selector, data distributor, numerical comparator, arithmetic/logic operation unit.

4.4.1 Encoder

1. Definition and working principle

• Using a binary code to represent information with a specific meaning is called encoding.
• A logic circuit with encoding function is called an encoder.
  

(1) Ordinary decoder (4-line-2-line encoder)

• 4 inputs$I_0{I}_1{I}_2{I}_3$, a high-level valid signal.
• 2 outputs$Y_1{Y}_0$。
• Premise: At any time,$I_0{I}_1{I}_2{I}_3$There can only be one value of 1. And there is a corresponding binary code$Y_1{Y}_0$。
• As shown in the following table, except for the 4 combinations of values ​​of the 4 inputs, the outputs corresponding to the other 12 combinations are all 00.

• Logical expressions and logic diagrams
  $Y_1=\overline{I_0}\overline{I_1}{I}_2\overline{I_3}+\overline{I_0}\overline{I_1}\overline{I_2}{I}_3$
  $Y_0=\overline{I_0}{I}_1\overline{I_2}\overline{I_3}+\overline{I_0}\overline{I_1}\overline{I_2}{I}_3$

• Additional question: If more than 2 of the 4 inputs have the value 1 at the same time, the output will be incorrectly encoded.
  For example:$I_2=I_3=1$hour,$Y_1{Y}_0=0$。
• To address this issue, you can increase priorities and set priorities.

(2) Priority encoder

• Based on the above, a truth table is listed.

• Logical expressions:
  $Y_1=I_2\overline{I_3}+I_3=I_2+I_3$
  $Y_0=I_1\overline{I_2}\overline{I_3}+I_3=I_1\overline{I_2}+I_3$

(3) Output value is valid

• Additional question: When$I_0=1or{I}_0=1$When, always$Y_1{Y}_0=0$. Different inputs, same outputs, indistinguishableValid output 0 ($I_0=1$）andInvalid output 0。
• To address this problem, we can add aOutput value is valid"The output flag value GS.
• For example, the 8421BCD encoder below. The first and second rows of the truth table are both 0000, which means that ABCD is a valid code only when GS==1.

2. Integrated circuit priority encoder

• Typical: CD4532 priority encoder (discontinued)
  

• $Priority\; encoder{I}_{7}The\; highest\; priority,I_{0}Lowest\; priority.$

  • The encoder works only when EI=1.
  • When EI=0, the encoder is prohibited from working (output is all low level).

• When EI=1, all inputs are low level and noLower priorityInput high level, then output 000. At this time, EO=1.

• EO = 1 only when EI = 1 and all inputs are 0. Dedicated to cascading with the EI of another device.

• When EI=1, at least one of the input terminals is high level 1, GS=1.

• For specific logical expressions and logic block diagrams, please refer to the book.

• $whenE{I}_1=0Time,\; piece1Disabled.Y_2{Y}_1{Y}_0==000，G{S}_1=0，E{O}_1=0。E{I}_0=0,piece0is\; also\; disabled.$

  • $at\; this\; timeG{S}_0=0。L_3{L}_2{L}_1{L}_0=0000。GS=G{S}_1+G{S}_0=0,$
  • This is an invalid encoding.

• $whenE{I}_1=1Time,\; piece1Encoding\; is\; allowed\; if{I}_{15}-I_8=\mathrm{000...000},at\; this\; timeE{O}_1=1,therebyE{I}_0=1.piece0Encoding\; is\; allowed.1Encoding\; takes\; precedence\; over\; slices0coding$。

  • $at\; this\; time{L}_3=G{S}_1=0，L2=Y{2}_1+Y{2}_0=Y{2}_0，L1=Y{1}_1+Y{1}_0=Y{1}_0，L0=Y{0}_1+Y{0}_0=Y{0}_0$。
  • $The\; output\; encoding\; range\; is0000-0111$。

• $whenE{I}_1=1Time,\; piece1Encoding\; is\; allowed\; if{I}_{15}-I_{8}at\; least\; one1,at\; this\; timeE{O}_1=0,therebyE{I}_0=0,piece0Encoding\; is\; prohibited.$

  • $at\; this\; time{L}_3=G{S}_1=1，L2=Y{2}_1+Y{2}_0=Y{2}_1，L1=Y{1}_1+Y{1}_0=Y{1}_1，L0=Y{0}_1+Y{0}_0=Y{0}_1$
  • $The\; output\; encoding\; range\; is1000-1111$。

4.4.2 Decoder

• 138 decoder.
• 151Data selector.

1. Definition and Function

• There are two types of decoders:
  • Unique address decoder: Converts a series of codes into valid signals that correspond to each other. (For example, a computer decodes the address of a storage unit, converts the address code into a valid signal, and selects the corresponding storage unit)
  • Code Converter: Converts one code into another.

(1) Binary decoder

• n input terminals
• $2^n$Output
• 1 enable terminal

(2) 2-wire to 4-wire decoder

• Output terminal, low level is effective
  
• Truth Table

• Logical expressions (NOT GateandNAND Gateexpression)

$\overline{Y_0}=\overline{\overline{\overline{E}}\cdot \overline{A_1}\cdot \overline{A_0}}$ //00
$\overline{Y_1}=\overline{\overline{\overline{E}}\cdot \overline{A_1}\cdot A_0}$ //01
$\overline{Y_2}=\overline{\overline{\overline{E}}\cdot A_1\cdot \overline{A_0}}$ //10
$\overline{Y_3}=\overline{\overline{\overline{E}}\cdot A_1\cdot A_0}$ //11

• Logic diagram of 2-wire to 4-wire decoder
  

2. Integrated circuit decoder

(1) Binary decoder

2-wire to 4-wire decoder x2

• 74x139 represents the CMOS type 74HC139 or the TTL type 74LS139.
• 74x139yes"Dual 2-wire to 4-wire decoder”。
• Two independent decoders are packaged in one integrated chip. (See above for details)
  

3-line to 8-line decoder

• 74x138 represents the CMOS type 74HC138 or the TTL type 74LS138.
• 74x138yes3-line to 8-line decoder。
• use3-line to 8-line decoderCan be composed4-line to 16-line decoder、5-line to 32-line decoder、6-line to 64-line decoder。
• when$E_3=1,\overline{E_2}=\overline{E_1}=0$The decoder is in working state.

• Following the previous text, the logical expression of "3-line to 8-line decoder" can be derived.

$\overline{Y_0}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot \overline{A_2}\cdot \overline{A_1}\cdot \overline{A_0}}$ //000
$\overline{Y_1}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot \overline{A_2}\cdot \overline{A_1}\cdot A_0}$ //001
$\overline{Y_2}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot \overline{A_2}\cdot A_1\cdot \overline{A_0}}$ //010
$\overline{Y_3}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot \overline{A_2}\cdot A_1\cdot A_0}$ //011
$\overline{Y_4}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot A_2\cdot \overline{A_1}\cdot \overline{A_0}}$ //100
$\overline{Y_5}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot A_2\cdot \overline{A_1}\cdot A_0}$ //101
$\overline{Y_6}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot A_2\cdot A_1\cdot \overline{A_0}}$ //110
$\overline{Y_7}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot A_2\cdot A_1\cdot A_0}$ //111

5-line to 32-line decoder

• Using 74x139 and 74x138 to form a "5-line to 32-line decoder"
  

3-wire to 8-wire decoder to implement logic functions

• The logic function is$L=\overline{A}\cdot \overline{C}+A\cdot B$
• The inputs of the 3-line to 8-line decoder can be defined as A, B, and C.
• The output of the 3-line to 8-line decoder is actually an 8-line output corresponding to the various minimum terms of A, B, and C.
• For any ABC combination, only one output will be at a valid level.
• L is actually a collection of several combinations of A, B, and C.

$L=\overline{A}\cdot \overline{C}+A\cdot B=\overline{A}\cdot \overline{B}\cdot \overline{C}+\overline{A}\cdot B\cdot \overline{C}+A\cdot B\cdot \overline{C}+ABC=m_0+m_2+m_6+m_7$

$\overline{Y_0}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot \overline{A_2}\cdot \overline{A_1}\cdot \overline{A_0}}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot m_0}$ //000
$\overline{Y_1}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot \overline{A_2}\cdot \overline{A_1}\cdot A_0}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot m_1}$ //001
$\overline{Y_2}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot \overline{A_2}\cdot A_1\cdot \overline{A_0}}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot m_2}$ //010
$\overline{Y_3}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot \overline{A_2}\cdot A_1\cdot A_0}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot m_3}$ //011
$\overline{Y_4}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot A_2\cdot \overline{A_1}\cdot \overline{A_0}}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot m_4}$ //100
$\overline{Y_5}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot A_2\cdot \overline{A_1}\cdot A_0}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot m_5}$ //101
$\overline{Y_6}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot A_2\cdot A_1\cdot \overline{A_0}}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot m_6}$ //110
$\overline{Y_7}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot A_2\cdot A_1\cdot A_0}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot m_7}$ //111

• $make\; sure{E}_3=1,E_2=0,E_1=0$, that is to say $\overline{Y_0}=\overline{m_0}，\overline{Y_2}=\overline{m_2}，\overline{Y_6}=\overline{m_6}，\overline{Y_7}=\overline{m_7}$。

• Transformation of the logistic function according to the inversion law
  $L=\overline{\overline{L}}=\overline{\overline{m_0+m_2+m_6+m_7}}=\overline{\overline{m_0}\cdot \overline{m_2}\cdot \overline{m_6}\cdot \overline{m_7}}=\overline{\overline{m_0+m_2+m_6+m_7}}=\overline{\overline{Y_0}\cdot \overline{Y_2}\cdot \overline{Y_6}\cdot \overline{Y_7}}$

• Get the logic diagram
  

(2) Binary-to-decimal decoder

• 774HC42

• 4 input ports

• 10 output terminals, output low level is valid, corresponding to decimal numbers 0~9.
  

• 4 input terminals, 16 conditions in total

• only$m_0,m_1,m_2......m_9$It is a valid input (the corresponding output pin outputs low 0, and the rest output high 1).

• The remaining 6$m_{10},m_{11},m_{12}......m_{15}$There is no valid decoding output (when invalid, all outputs are high 1).

• Draw the input and output waveforms of 74HC42.

• If DCBA inputs 0000-1001 in a loop,$\overline{Y_0}arrive\overline{Y_9}$The upper cycle outputs a "sequential pulse signal".
• The decoder can be constructedSequential pulseGenerate circuit.
  

(3) Seven-segment display decoder

• Digital tube display principle
  

• Integrated seven-segment display decoder. 74HC4511 (common cathode) (high level lights up)

• $LE$Latch Enable

• $\overline{LT}$Lamp test input, when$\overline{LT}=0$When , ag outputs all 1s and displays the character "8".

• $\overline{BL}$Light off input, when$\overline{LT}=1,and\overline{BL}=1$When , ag outputs all 0. It can be used to turn off unnecessary displayed zero "0".
  

• $D_3{D}_2{D}_1{D}_0$=0000, the corresponding output character is "0"

• $D_3{D}_2{D}_1{D}_0$=0001, the corresponding output character is "1"

• $D_3{D}_2{D}_1{D}_0$=0010, the corresponding output font is "2"

• $D_3{D}_2{D}_1{D}_0$=0011, the corresponding output character is "3"

• $D_3{D}_2{D}_1{D}_0$=0100, the corresponding output font is "4"

• $D_3{D}_2{D}_1{D}_0$=0101, the corresponding output character is "5"

• $D_3{D}_2{D}_1{D}_0$=0110, the corresponding output character is "6"

• $D_3{D}_2{D}_1{D}_0$=0111, the corresponding output character is "7"

• $D_3{D}_2{D}_1{D}_0$=1000, the corresponding output font is "8"

• $D_3{D}_2{D}_1{D}_0$=1001, the corresponding output font is "9"

• 1010-1111, off

3. Data Allocator

• One to many, send the data of the public data line to different channels as needed.

• Similar to "SPMT switch"

• Using unique address decoder to implement data distributor

• For example, 74x138 integrates a 3-line to 8-line decoder.

• $\overline{E_1}As\; data\; input$

• $Y_0{Y}_1{Y}_2{Y}_3{Y}_4{Y}_5{Y}_6{Y}_7$8 channels as data output
  

• $\overline{Y_2}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot \overline{A_2}\cdot A_1\cdot \overline{A_0}}$ //010

• Above,$E_3=1，\overline{E_2}=0$, when the address line$A_2{A}_1{A}_0=010$hour,$\overline{Y_2}=\overline{E_1}$

• Similarly, we can conclude that:
  When the address line$A_2{A}_1{A}_0=000$hour,$\overline{Y_0}=\overline{E_1}=D$,other$Y_x=1$。
  When the address line$A_2{A}_1{A}_0=001$hour,$\overline{Y_1}=\overline{E_1}=D$,other$Y_x=1$。
  When the address line$A_2{A}_1{A}_0=010$hour,$\overline{Y_2}=\overline{E_1}=D$,other$Y_x=1$。
  When the address line$A_2{A}_1{A}_0=011$hour,$\overline{Y_3}=\overline{E_1}=D$,other$Y_x=1$。
  When the address line$A_2{A}_1{A}_0=100$hour,$\overline{Y_4}=\overline{E_1}=D$,other$Y_x=1$。
  When the address line$A_2{A}_1{A}_0=101$hour,$\overline{Y_5}=\overline{E_1}=D$,other$Y_x=1$。
  When the address line$A_2{A}_1{A}_0=110$hour,$\overline{Y_6}=\overline{E_1}=D$,other$Y_x=1$。
  When the address line$A_2{A}_1{A}_0=111$hour,$\overline{Y_7}=\overline{E_1}=D$,other$Y_x=1$。

4.4.3 Data Selector

1. Definition and Function

• This has the opposite function to the "data distributor" in 4.4.2.3 above.
• More to one.
• For example, a 4-to-1 data selector.
  
• $\overline{E}=0$, allowed to work.
• when$S_1=0，S_0=0$hour,$Y=I_0$
• when$S_1=0，S_0=1$hour,$Y=I_1$
• when$S_1=1，S_0=0$hour,$Y=I_2$
• when$S_1=1，S_0=1$hour,$Y=I_3$

2. Integrated circuit data selector

• 74x151: One-to-8-to-1 data selector. Corresponds to CMOS type 74HC151, TTL type 74LS151.
• 74x153: Dual 4-to-1 data selector. Corresponds to CMOS type 74HC153, TTL type 74LS153.
• 74x157: Quad-2-to-1 data selector. Corresponds to CMOS type 74HC157, TTL type 74LS157.
• 74x251: With three-state output, when$\overline{E}=1$When the chip output is high impedance.Line and”。
• 74x253: With three-state output, when$\overline{E}=1$When the chip output is high impedance.Line and”。
• 74x257: With three-state output, when$\overline{E}=1$When the chip output is high impedance.Line and”。

（1）74HC151

$Y=\overline{S_2}\cdot \overline{S_1}\cdot \overline{S_0}\cdot D_0+\overline{S_2}\cdot \overline{S_1}\cdot S_0\cdot D_1+\overline{S_2}\cdot S_1\cdot \overline{S_0}\cdot D_2+\overline{S_2}\cdot S_1\cdot S_0\cdot D_3+S_2\cdot \overline{S_1}\cdot \overline{S_0}\cdot D_4+S_2\cdot \overline{S_1}\cdot S_0\cdot D_5+S_2\cdot S_1\cdot \overline{S_0}\cdot D_6+S_2\cdot S_1\cdot S_0\cdot D_7$

(2) Application of data selector

• Extensions to data selectors.

  • Output bit expansion ($Y_0->Y_1{Y}_0$)
  • Input digit expansion ($D_7{D}_6{D}_5{D}_4{D}_3{D}_2{D}_1{D}_0->D_{15}{D}_{14}{D}_{13}{D}_{12}{D}_{11}{D}_{10}{D}_9{D}_8{D}_7{D}_6{D}_5{D}_4{D}_3{D}_2{D}_1{D}_0$）。

• Logical Function Generator

  • Known, 8 to 1 data selector.
    $Y=\overline{S_2}\cdot \overline{S_1}\cdot \overline{S_0}\cdot D_0+\overline{S_2}\cdot \overline{S_1}\cdot S_0\cdot D_1+\overline{S_2}\cdot S_1\cdot \overline{S_0}\cdot D_2+\overline{S_2}\cdot S_1\cdot S_0\cdot D_3+S_2\cdot \overline{S_1}\cdot \overline{S_0}\cdot D_4+S_2\cdot \overline{S_1}\cdot S_0\cdot D_5+S_2\cdot S_1\cdot \overline{S_0}\cdot D_6+S_2\cdot S_1\cdot S_0\cdot D_7$

  • $Y=m_0\cdot D_0+m_1\cdot D_1+m_2\cdot D_2+m_3\cdot D_3+m_4\cdot D_4+m_5\cdot D_5+m_6\cdot D_6+m_7\cdot D_7$

  • Logical functions$L=\overline{A}BC+A\overline{B}C+AB$
    $L=\overline{A}BC+A\overline{B}C+AB=\overline{A}BC+A\overline{B}C+AB\overline{C}+ABC=m_3+m_5+m_6+m_7$

  • Use 8 to 1 data selector to implement the above function L
    $L=Y=m_3+m_5+m_6+m_7,in{D}_7{D}_6{D}_5{D}_3=1111，D_4{D}_2{D}_1{D}_0=0000$
    

• Parallel data to serial data
  

4.4.4 Numeric Comparator

1. Definition and Function

• Compare the size of two numbers.

(1) 1-bit numerical comparator

• List the truth table

• Logical expressions
  • $F_{A>B}=A\cdot \overline{B}$
  • $F_{A<B}=\overline{A}\cdot B$
  • $F_{A==B}=A\cdot B+\overline{A}\cdot \overline{B}$
• Logic diagram
  

(2) 2-bit numerical comparator

• List the truth table

• Logical expressions
  $F_{A>B}=F_{A_1>B_1}+F_{A_1==B_1}\cdot F_{A_0>B_0}$
  $F_{A<B}=F_{A_1<B_1}+F_{A_1==B_1}\cdot F_{A_0<B_0}$
  $F_{A==B}=F_{A_1==B_1}\cdot F_{A_0==B_0}$

• Logic diagram
  

2. Integrated numerical comparator

• 74x85, 4-bit numerical comparator. (CMOS type 74HC85)
• 74x682, 8-bit numerical comparator.

(1) Functions of 74HC85

• $I_{A>B}、I_{A=B}、I_{A<B}$It is the extended input terminal. When the 4-bit input AB is equal, the size of AB is determined based on the extended input terminal.
  
• You can write logical expressions by listing the truth table.

(2) Expansion of the number of bits of numerical comparator

• Connect in series to expand to 8-bit value comparator
  

• Connect in parallel and expand to a 16-bit numerical comparator.

• When connected in parallel, the speed is fast.
  

The article is limited in length. Please refer to "【Study Notes】4. Combinational Logic Circuits (Part 2)" for the follow-up.