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• Divisio circuli digitalis: logica iunctura gyrorum, logica circuli sequentialis.
• Hoc capitulum studet circulis logicalibus combinationis.

4.1 Analysis Logicae Circuituum deductorum

• Posita logica circuitio, eius expressionem logicam definire, mensam veritatis enumerare, expressionem logicam simpliciorem obtine, eiusque munus resolvere.

III, frenum impar pari circuitu

(1) Ut patet in figura infra.

(2) Verum mensam List

(III) de AnalyzeImpares pari ambituOfficium.

• Quando C est 1, et in AB idem sunt 0 vel 2 1s (AB, Z=0), (imparium 1s), L est 1s.
• Quando C est 0, et in AB una tantum est (AB alia, Z=1), (inpar numerus 1s), L est 1;
• Id est, cum impar numerus 1's in ABC sunt, L 1 est. Cum numerus sit par 1 s in ABC, L est 0 .

III-bit etiam pari circuitu

(1) Ex pari ambitu impari, addito inverto ad output finem, accipere possumusEtiam pari ambitu。

III-bit complementum circuitu

• Ut infra patebit.
  
• Dictio logica.
  $X=A$
  $Y=\overline{(\overline{A\cdot \overline{B}})\cdot (\overline{\overline{A}\cdot B)}}=A\cdot \overline{B}+\overline{A}\cdot B$
  $Z=\overline{(\overline{\overline{A}\cdot C})\cdot (\overline{A\cdot \overline{C})}}=\overline{A}\cdot C+A\cdot \overline{C}$
• Mensae veritatis.

• Eget Analysis.
  (1) Codicem originale ABC, A est signum frenum, 0 numerum positivum repraesentat, et 1 numerus negativum repraesentat.
  (2) Inverso codice XYZ, X signo bis servato, consentaneum est A.
  (3) Cum A=0 numerus affirmativus est, YZ et BC constantes sunt.
  (4) Cum A=1 numerus negativus est, signum frenum mutatur in X=A, et YZ ex invertendo BC.

4.2 Distinctio logicae circuli design

• Munus logicum declara, initus et output determinare, tabulam veritatis enumerare, expressionem logicam scribere, expressionem logicam transformationem simpliciorem reddere ac logicam schema.

III-digiti agmen adventus indicator lux

• necessitudo.
  (1) Use 2 initsNAND porta,invertere.
  (2) N. 1 indicator lumen, exprime agmen adventus, indicator lumen. Princeps prior.
  (3) N. 2 indicator lumen, directum, expressum agmen introitus stationis indicator lumen. In prioritate.
  (4) N. 3 indicator lumen, tardum agmen intrans, statio indicator lucis. Humilis prioritas.
  (5) In uno signo plus lucis simul esse potest.

• Definire initus et output variabiles.
  (1) Input signum;${ego}_{0}expresse\; rogamus\; ;{ego}_{1}Mox\; pete\; cito;{ego}_{2}Patiens\; agmen\; petitio$ . 1 means there is an inbound request, 0 means there is no inbound request.
  (2) Output signum,$L_{0}Exprime\; adventus\; lucis;L_{1}Dirige\; siste\; indicator\; lumen;L_{2}Tardum\; agmen\; adventus\; indicator\; lux$ . I lux significat in, 0 significat lux est off.

• Mensae veritatis.

• Logicas notas
  $L_0={ego}_0$
  $L_1=\overline{{ego}_0}\cdot {ego}_1$
  $L_2=\overline{{ego}_0}\cdot \overline{{ego}_1}\cdot {ego}_2$

• Convertere ad NAND forma Quod erat faciendum.
  $L_0={ego}_0$
  $L_1=\overline{\overline{\overline{{ego}_0}\cdot {ego}_1}}$
  $L_2=\overline{\overline{\overline{\overline{\overline{{ego}_0}\cdot \overline{{ego}_1}}}\cdot {ego}_2}}$

• Diagramma trahunt logicam.
  (1) DOLO 74HC00 continet quattuor 2-input CMOS NAND portas.
  (2) DOLO 74HC04 continet 6 CMOS inverters.
  

Converte IV-bit Grey codice ad naturalem binarii codice

• necessitudo.
  (1) Quaelibet porta logicae ambitus adhiberi potest.
  (2) Grajum codicem 4-bit, in codicem binarium naturalem conversum.

• Definire initus et output variabiles.
  (1) Input variabilium$G_3,G_2,G_1,G_0$。
  (2) Output variabilium$B_3,B_2,B_1,B_0$。

• Enumerare mensam veritatis.

• Karnaugh tabula trahunt a veritate fundatur in mensa.
  
  

• Indices dictionum logicalium.
  $B_3=G_3$
  $B_2=\overline{G_3}\cdot G_2+G_3\cdot \overline{G_2}=G_3\oplus G_2$
  $B_1=\overline{G_3}{G}_2\overline{G_1}+G_3\overline{G_2}\overline{G_1}+\overline{G_3}\overline{G_2}{G}_1+G_3{G}_2{G}_1=(G_3\overline{G_2}+\overline{G_3}{G}_2)\overline{G_1}+\overline{(G_3\overline{G_2}+\overline{G_3}{G}_2)}{G}_1=G_3\oplus G_2\oplus G_1$
  $B_0=G_3\oplus G_2\oplus G_1\oplus G_0$

• Diagramma trahunt logicam.
  

4.3 Competition et casus in logicis combinationalibus circuitibus

• In logica combinatione circuitibus certum temporis spatium accipit per portas logicas signa transire.
• Signa per vias varias vadunt et tempora transmissionum diversorum habent (diuersitates portarum logicarum, diversa genera portarum logicarum).
• Competition: Signum in multiplicibus input terminalibus portae logicae in contrarias partes mutatur simul et mutatio temporis differt. (Qui prius mutat, et qui postea mutat, certat).
• Haunting: Contentio pulsus angustos interventus output producit, phaenomenon Haunting notum.

4.3.1 Rationes competitive periculorum

• Signorum initus simul pervenire non potest, unde in brevi tempore pulsus enormis angustus.
• ET PORTAE
  
• VEL porta
  

4.3.2 Ratio competitive periculum ad tollendum

1. Reveles et eliminare terminorum multiplicationem complementariam

• $F=(A+B)(\overline{A}+C)$
• Cum B=C=0, apparebit$A\overline{A}$producto termino.
• Reperire:$A\overline{A}$Producta verba ad "periculum genus" ducere possunt.
  
• Multiplicatio terminorum comple- riorum: $A\cdot \overline{A}$。
• Eliminare: $F=(A+B)(\overline{A}+C)=A\overline{A}+AC+B\overline{A}+BC=AC+B\overline{A}+BC$ . Hoc modo complementaria nulla sunt, et quodammodo vitantur certatio et periculum captivitatis.

2. Verba producta addere ne addendo verba complementaria

• Ut supra,$F=AC+B\overline{A}+BC$quando B=C=1;$F=A+\overline{A}+1=1$ . BC producti terminus hic = 1 munus gerit in vitando periculum certationis in additis terminis complementariis.
• secundumCommuniter identitatis "OR" res(Sectio 2.1).$AB+\overline{A}C+BC=AB+\overline{A}C$。
• Cum occurrant munera logica$L=AC+B\overline{C}$In hac forma addere possumus terminum producti$AB$。
  

3. Parallel capacitor ad output

• Tardius enim labor missionibus.
• Valor capacitas est 4~20pF. Partes "lenis" ludit in pulsus angustis periclitatur.
• Incommodum: Ortus et cadens marginibus output waveformi tardius fiet.

4.4 (Cognita focus) Plures logicae typicae combinationis ambitus integratae

• Encoder, decoder, notitia selector, data distributor, comparator numeralis, operatio arithmetica/logica unitas.

4.4.1 Encoder

1. Definitio et opus principium

• Utens codice binario ad informationes repraesentandas cum certa significatione descriptam appellatur.
• Logica circuli functione modum translitterandi vocatur encoder.
  

(1) decoder Ordinarium (4-filum-2-filum encoder)

• 4 inputs${ego}_0{ego}_1{ego}_2{ego}_3$summus gradus activum signum.
• 2 outputs$Y_1{Y}_0$。
• Praemissa: aliquando;${ego}_0{ego}_1{ego}_2{ego}_3$ Unius valoris 1 esse potest.Et adest in codice binario respondente$Y_1{Y}_0$。
• Ut in tabula infra ostendetur, praeter quattuor compositiones valorum quattuor inituum, outputs aliis 12 complexionibus respondentes omnes 00 sunt.

• Locutiones logicae et diagrammata logica
  $Y_1=\overline{{ego}_0}\overline{{ego}_1}{ego}_2\overline{{ego}_3}+\overline{{ego}_0}\overline{{ego}_1}\overline{{ego}_2}{ego}_3$
  $Y_0=\overline{{ego}_0}{ego}_1\overline{{ego}_2}\overline{{ego}_3}+\overline{{ego}_0}\overline{{ego}_1}\overline{{ego}_2}{ego}_3$

• Addita quaestio: Si plus quam 2 ex 4 inputibus valorem 1 simul habent, output non recte encoded erit.
  Exempli gratia:${ego}_2={ego}_3=1$hora;$Y_1{Y}_0=0$。
• Ad hoc problema, prioritates ac prioritates institui possunt prioritate augendo.

(2) Encoder prioritate

• Fundatur supra, verum mensam enumerare.

• Locutio logica:
  $Y_1={ego}_2\overline{{ego}_3}+{ego}_3={ego}_2+{ego}_3$
  $Y_0={ego}_1\overline{{ego}_2}\overline{{ego}_3}+{ego}_3={ego}_1\overline{{ego}_2}+{ego}_3$

(III) valorem valet quod output

• Extra quaestionem: quando${ego}_0=1or\; *{ego}_0=1$semper, semper$Y_1{Y}_0=0$ .Inputationes variae, eiusdem outputes, indiscretaeValidum output est 0 (${ego}_0=1$）etAliquam output 0。
• Ad hanc quaestionem solvendam, expressionem addere potes "In output valorem valet"De valore vexillum output est GS.
• Exempli gratia, sequentia 8421BCD encoder. Primus et secundus ordines veritatis tabulae sunt 0000. Tantum cum GS=1, significat ABCD hoc tempore codicem validum esse.

2. Integrated circuitu prioritas encoder

• Typical: CD4532 encoder prioritas (discontinuata)
  

• $prioritas\; encoder{ego}_{7}summa\; prioritas;{ego}_{0}Ima\; prioritas.$

  • Solum cum EI=1, encoder operatur.
  • Cum EI=0, encoder laborare prohibetur (outputus totus est humilis gradus).

• Cum EI = I, quando omnes inputationes humiles sunt, ninferiore prius Input magna massa, ac tempus ante 000 output. Hoc tempore EO=1.

• Solum cum EI=1 et inputationes omnes sunt 0, EO = 1; Dicata EI lapsus cum alia fabrica.

• Quando EI=1, saltem alter initus terminalum alta est 1, et GS=1.

• Quaeso ad librum referri ad expressiones logicas specificas et schemata truncum logicum.

• $quandoE{ego}_1=0tempus,\; film1Debilis.Y_2{Y}_1{Y}_0==000，G{S}_1=0，E{O*******}_1=0。E{ego}_0=0,\; piece0Item\; debilis.$

  • $hoc\; temporeG{S}_0=0。L_3{L}_2{L}_1{L}_0=0000。GS=G{S}_1+G{S}_0=0,$
  • Haec descriptam aeger est.

• $quandoE{ego}_1=1tempus,\; film1Licet\; modum\; translitterandi,\; si{ego}_{15}-{ego}_8=\mathrm{000...000},hoc\; temporeE{O*******}_1=1,\; itaE{ego}_0=1.piece0Delatam\; permissum\; est.Ex\; his\; videri\; potest\; quod\; amet1Encoding\; habet\; prioritatem\; peragitato0coding$。

  • $hoc\; tempore{L}_3=G{S}_1=0，L2=Y{2}_1+Y{2}_0=Y{2}_0，L1=Y{1}_1+Y{1}_0=Y{1}_0，L0=Y{0}_1+Y{0}_0=Y{0}_0$。
  • $Output\; modum\; translitterandi\; range\; est0000-0111$。

• $quandoE{ego}_1=1tempus,\; film1Licet\; modum\; translitterandi,\; si{ego}_{15}-{ego}_{8}saltem\; unum1,hoc\; temporeE{O*******}_1=0,itaE{ego}_0=0,\; piece0Delatam\; esse\; prohibitam.$

  • $hoc\; tempore{L}_3=G{S}_1=1，L2=Y{2}_1+Y{2}_0=Y{2}_1，L1=Y{1}_1+Y{1}_0=Y{1}_1，L0=Y{0}_1+Y{0}_0=Y{0}_1$
  • $Output\; modum\; translitterandi\; range\; est1000-1111$。

4.4.2 Decoder

• 138 decodum.
• 151 data selecta.

1. Definitio et munus

• Decoderum genera duo sunt:
  • Singularis inscriptionis decoder: seriei notarum in signum validum quod uni correspondet, convertit. (Exempli gratia, computatorium inscriptionis unitatis repono, codicem inscriptionis in signum validum convertit et congruentem unitas repono deligit)
  • Transcoder: unum codicem in alium codicem convertit.

(1) Binarii decoder

• n initus terminales
• $2^n$output terminatio
• I enable terminatio

(2) 2-filum-4-filum decoder

• Output terminatio activa iaces
  
• veritas mensa

• expressio logica (NON portaetNAND portaforma expressio)

$\overline{Y_0}=\overline{\overline{\overline{E}}\cdot \overline{A_1}\cdot \overline{A_0}}$ //00
$\overline{Y_1}=\overline{\overline{\overline{E}}\cdot \overline{A_1}\cdot A_0}$ //01
$\overline{Y_2}=\overline{\overline{\overline{E}}\cdot A_1\cdot \overline{A_0}}$ //10
$\overline{Y_3}=\overline{\overline{\overline{E}}\cdot A_1\cdot A_0}$ //11

• Logica schematis 2-filum ad 4-filum decoder
  

2. Integrated ambitu decoder

(1) Binarii decoder

2-filum 4-filum decoder x2

• Utere 74x139 ut indicant CMOS typus 74HC139 vel TTL typus 74LS139.
• 74x139Etiam"Dual 2-filum ad 4-filum decoder”。
• Duo decoders independentes in uno spumae integrali fasciculi sunt. (vide supra ad singula)
  

III-filum ad VIII-filum decoder

• Utere 74x138 ad repraesentandum CMOS typus 74HC138 vel TTL typus 74LS138.
• 74x138sicIII-filum ad VIII-filum decoder。
• ususIII-filum ad VIII-filum decoderpotestIV-linea ad XVI-linea decoder、5-line to 32-line decoder、6-line to 64-line decoder。
• quando$E_3=1,\overline{E_2}=\overline{E_1}=0$decoda laborat conditio.

• Post articulum praecedentem, logica expressio "3-line-8-lineae decoder" derivari potest.

$\overline{Y_0}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot \overline{A_2}\cdot \overline{A_1}\cdot \overline{A_0}}$ //000
$\overline{Y_1}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot \overline{A_2}\cdot \overline{A_1}\cdot A_0}$ //001
$\overline{Y_2}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot \overline{A_2}\cdot A_1\cdot \overline{A_0}}$ //010
$\overline{Y_3}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot \overline{A_2}\cdot A_1\cdot A_0}$ //011
$\overline{Y_4}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot A_2\cdot \overline{A_1}\cdot \overline{A_0}}$ //100
$\overline{Y_5}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot A_2\cdot \overline{A_1}\cdot A_0}$ //101
$\overline{Y_6}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot A_2\cdot A_1\cdot \overline{A_0}}$ //110
$\overline{Y_7}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot A_2\cdot A_1\cdot A_0}$ //111

5x-32 line decoder

• Utere 74x139 et 74x138 formare "5-linea 32-linea decoder"
  

3-filum ad 8-filum decoder instrumenti logicae functionis

• Munus rationis est$L=\overline{A}\cdot \overline{C}+A\cdot B$
• Inputatio 3-lineae ad 8-lineam decoder definiri potest ut A, B, C;
• Procuratio lineae 3-ad 8-lineae decoder est actu 8-linea outputa variis terminis minimis A, B, C respondens.
• Pro quavis compositione ABC, una tantum output in gradu valido erit.
• L actu collectio plurium combinationum A, B, C.

$L=\overline{A}\cdot \overline{C}+A\cdot B=\overline{A}\cdot \overline{B}\cdot \overline{C}+\overline{A}\cdot B\cdot \overline{C}+A\cdot B\cdot \overline{C}+ABC=m_0+m_2+m_6+m_7$

$\overline{Y_0}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot \overline{A_2}\cdot \overline{A_1}\cdot \overline{A_0}}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot m_0}$ //000
$\overline{Y_1}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot \overline{A_2}\cdot \overline{A_1}\cdot A_0}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot m_1}$ //001
$\overline{Y_2}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot \overline{A_2}\cdot A_1\cdot \overline{A_0}}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot m_2}$ //010
$\overline{Y_3}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot \overline{A_2}\cdot A_1\cdot A_0}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot m_3}$ //011
$\overline{Y_4}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot A_2\cdot \overline{A_1}\cdot \overline{A_0}}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot m_4}$ //100
$\overline{Y_5}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot A_2\cdot \overline{A_1}\cdot A_0}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot m_5}$ //101
$\overline{Y_6}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot A_2\cdot A_1\cdot \overline{A_0}}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot m_6}$ //110
$\overline{Y_7}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot A_2\cdot A_1\cdot A_0}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot m_7}$ //111

• $face\; certum{E}_3=1,E_2=0,E_1=0$, id est, narrantur $\overline{Y_0}=\overline{m_0}，\overline{Y_2}=\overline{m_2}，\overline{Y_6}=\overline{m_6}，\overline{Y_7}=\overline{m_7}$。

• Munera logicam transformare secundum legis inversionem
  $L=\overline{\overline{L}}=\overline{\overline{m_0+m_2+m_6+m_7}}=\overline{\overline{m_0}\cdot \overline{m_2}\cdot \overline{m_6}\cdot \overline{m_7}}=\overline{\overline{m_0+m_2+m_6+m_7}}=\overline{\overline{Y_0}\cdot \overline{Y_2}\cdot \overline{Y_6}\cdot \overline{Y_7}}$

• Accipere logica tabula
  

(2) Binarii decimales decoder

• 774HC42

• 4 inputs

• 10 output terminals, output active in plano humilis, numeris decimalibus 0~9.
  

• 4 input terminales, summa 16 condicionum

• solum$m_0,m_1,m_2......m_9$Validum est initus (in outputs pin outputs correspondentes low 0, et ceterae outputes altae sunt 1).

• Inter reliquas 6$m_{10},m_{11},m_{12}......m_{15}$Significat nullum esse validum decoding output (cum invalidum est, output est omne altum 1).

• Trahe input et output waveform diagrams of 74HC42.

• Si DCBA ansa inputs 0000-1001, erit$\overline{Y_0}venire\overline{Y_9}$Superior ansa outputs "sequential pulsus signum".
• In decoder construi potestordo pulsusCircuitus generate.
  

(III) septem ostentationem decoder segmentum

• Digital tube display principle
  

• Integrated septem- segmentum propono decoder. 74HC4511 (cathode communis) (altum gradum illuminat);

• $LE$Claustrum enable

• $\overline{LT}$lucerna test initus cum$\overline{LT}=0$Cum , ag outputs omnia 1 et ostendit fontem "8".

• $\overline{BL}$Lux off initus, cum$\overline{LT}=1,et\overline{BL}=1$ Cum , ag outputs omnes 0 . Exstinguere potest adhiberi superflua nulla "0" ostendi.
  

• $D_3{D}_2{D}_1{D}_0$= 0000, congruens output glyph "0"

• $D_3{D}_2{D}_1{D}_0$=0001, output fontium respondentis "I"

• $D_3{D}_2{D}_1{D}_0$=0010, output fontis respondentis "2"

• $D_3{D}_2{D}_1{D}_0$=0011, output fontis respondentis "3"

• $D_3{D}_2{D}_1{D}_0$= 0100, output fontis respondentis "4"

• $D_3{D}_2{D}_1{D}_0$= 0101, output fontis respondentis "5"

• $D_3{D}_2{D}_1{D}_0$=0110, output fontis respondentis "6"

• $D_3{D}_2{D}_1{D}_0$=0111, output fontis respondentis "7"

• $D_3{D}_2{D}_1{D}_0$= 1000, output respondens font "8"

• $D_3{D}_2{D}_1{D}_0$=1001, fontis output respondentis "9"

• 1010-1111, off

3. Data distributor

• Ab uno ad plures, linea data in communi notitia ad diversos canales prout opus est mittitur.

• Similia cum "uno polo multithrow switch"

• Singulari inscriptione decoder utens, notitia allocator efficiendum

• Pro exemplo, 74x138 3-linea ad 8-lineam decoder integrat.

• $\overline{E_1}ut\; data\; initus$

• $Y_0{Y}_1{Y}_2{Y}_3{Y}_4{Y}_5{Y}_6{Y}_7$VIII channels sicut notitia output
  

• $\overline{Y_2}=\overline{E_3\cdot \overline{\overline{E_2}}\cdot \overline{\overline{E_1}}\cdot \overline{A_2}\cdot A_1\cdot \overline{A_0}}$ //010

• Supra pictam;$E_3=1，\overline{E_2}=0$Cum oratio recta$A_2{A}_1{A}_0=010$hora;$\overline{Y_2}=\overline{E_1}$

• Per idem concludere possumus:
  Cum oratio recta$A_2{A}_1{A}_0=000$hora;$\overline{Y_0}=\overline{E_1}=D$, alius$Y_{x**************************************************************************************************************************************************************************************}=1$。
  Cum oratio recta$A_2{A}_1{A}_0=001$hora;$\overline{Y_1}=\overline{E_1}=D$, alius$Y_{x**************************************************************************************************************************************************************************************}=1$。
  Cum oratio recta$A_2{A}_1{A}_0=010$hora;$\overline{Y_2}=\overline{E_1}=D$, alius$Y_{x**************************************************************************************************************************************************************************************}=1$。
  Cum oratio recta$A_2{A}_1{A}_0=011$hora;$\overline{Y_3}=\overline{E_1}=D$, alius$Y_{x**************************************************************************************************************************************************************************************}=1$。
  Cum oratio recta$A_2{A}_1{A}_0=100$hora;$\overline{Y_4}=\overline{E_1}=D$, alius$Y_{x**************************************************************************************************************************************************************************************}=1$。
  Cum oratio recta$A_2{A}_1{A}_0=101$hora;$\overline{Y_5}=\overline{E_1}=D$, alius$Y_{x**************************************************************************************************************************************************************************************}=1$。
  Cum oratio recta$A_2{A}_1{A}_0=110$hora;$\overline{Y_6}=\overline{E_1}=D$, alius$Y_{x**************************************************************************************************************************************************************************************}=1$。
  Cum oratio recta$A_2{A}_1{A}_0=111$hora;$\overline{Y_7}=\overline{E_1}=D$, alius$Y_{x**************************************************************************************************************************************************************************************}=1$。

4.4.3 Data Selector

1. Definitio et munus

• Munus oppositum est "data allocatori" in 4.4.2.3 supra.
• Multi ad unum.
• Exempli gratia, 4-ad-1 data selecta.
  
• $\overline{E}=0$permissum facere.
• quando$S_1=0，S_0=0$hora;$Y={ego}_0$
• quando$S_1=0，S_0=1$hora;$Y={ego}_1$
• quando$S_1=1，S_0=0$hora;$Y={ego}_2$
• quando$S_1=1，S_0=1$hora;$Y={ego}_3$

2. Integrated circuitu notitia electrix

• 74x151 : 1-8-SLECTO-DATA SELECTA. Respondet CMOS typus 74HC151 et TTL typus 74LS151.
• 74x153 : Dual-4-ad-I-DATA SELECTA. Respondet CMOS typus 74HC153 et TTL typus 74LS153.
• 74x157: Quattuor ad duos ad unum data selecta. Respondet CMOS typus 74HC157 et TTL typus 74LS157.
• 74x251 : Cum tri-statu output, quando$\overline{E}=1$ coacervatum est in statu summo impedimento. Suscipe plures chip outputs "Line and”。
• 74x253: Cum tri-statu output, quando$\overline{E}=1$ coacervatum est in statu summo impedimento. Suscipe plures chip outputs "Line and”。
• 74x257: Cum tri-statu output, quando$\overline{E}=1$ coacervatum est in statu summo impedimento. Suscipe plures chip outputs "Line and”。

1）74HC151

$Y=\overline{S_2}\cdot \overline{S_1}\cdot \overline{S_0}\cdot D_0+\overline{S_2}\cdot \overline{S_1}\cdot S_0\cdot D_1+\overline{S_2}\cdot S_1\cdot \overline{S_0}\cdot D_2+\overline{S_2}\cdot S_1\cdot S_0\cdot D_3+S_2\cdot \overline{S_1}\cdot \overline{S_0}\cdot D_4+S_2\cdot \overline{S_1}\cdot S_0\cdot D_5+S_2\cdot S_1\cdot \overline{S_0}\cdot D_6+S_2\cdot S_1\cdot S_0\cdot D_7$

(II) applicatione data electrix

• Extensiones pro notitia selectorum.

  • Extensio aliquantulus output ($Y_0->Y_1{Y}_0$)
  • Input extensio digit ($D_7{D}_6{D}_5{D}_4{D}_3{D}_2{D}_1{D}_0->D_{15}{D}_{14}{D}_{13}{D}_{12}{D}_{11}{D}_{10}{D}_9{D}_8{D}_7{D}_6{D}_5{D}_4{D}_3{D}_2{D}_1{D}_0$）。

• logice munus generantis

  • Notum, 8- ad-I Data SELECTA.
    $Y=\overline{S_2}\cdot \overline{S_1}\cdot \overline{S_0}\cdot D_0+\overline{S_2}\cdot \overline{S_1}\cdot S_0\cdot D_1+\overline{S_2}\cdot S_1\cdot \overline{S_0}\cdot D_2+\overline{S_2}\cdot S_1\cdot S_0\cdot D_3+S_2\cdot \overline{S_1}\cdot \overline{S_0}\cdot D_4+S_2\cdot \overline{S_1}\cdot S_0\cdot D_5+S_2\cdot S_1\cdot \overline{S_0}\cdot D_6+S_2\cdot S_1\cdot S_0\cdot D_7$

  • $Y=m_0\cdot D_0+m_1\cdot D_1+m_2\cdot D_2+m_3\cdot D_3+m_4\cdot D_4+m_5\cdot D_5+m_6\cdot D_6+m_7\cdot D_7$

  • logice munus$L=\overline{A}BC+A\overline{B}C+AB$
    $L=\overline{A}BC+A\overline{B}C+AB=\overline{A}BC+A\overline{B}C+AB\overline{C}+ABC=m_3+m_5+m_6+m_7$

  • Utere 8-ad-1 data electrix ad effectum deducendi supra munus L
    $L=Y=m_3+m_5+m_6+m_7,in{D}_7{D}_6{D}_5{D}_3=1111，D_4{D}_2{D}_1{D}_0=0000$
    

• Vide data ad parallel data
  

4.4.4 Numericorum comparator

1. Definitio et munus

• Confer magnitudinem duorum numerorum.

(1) 1-digiti numeralis comparator

• Album mensa veritas

• logica expressio
  • $F_{A>B}=A\cdot \overline{B}$
  • $F_{A<B}=\overline{A}\cdot B$
  • $F_{A==B}=A\cdot B+\overline{A}\cdot \overline{B}$
• logica tabula
  

(2) 2-digiti comparator numeralis

• Album mensa veritas

• logica expressio
  $F_{A>B}=F_{A_1>B_1}+F_{A_1==B_1}\cdot F_{A_0>B_0}$
  $F_{A<B}=F_{A_1<B_1}+F_{A_1==B_1}\cdot F_{A_0<B_0}$
  $F_{A==B}=F_{A_1==B_1}\cdot F_{A_0==B_0}$

• logica tabula
  

2. Integrated comparator numeralis

• 74x85, 4-bit comparator numeralis. (CMOS type 74HC85)
• 74x682, 8-bit comparator numeralis.

(1) functiones 74HC85

• ${ego}_{A>B}、{ego}_{A=B}、{ego}_{A<B}$ Expansio initus est terminatio. Cum inputibus 4-angulis AB omnes aequales sint, magnitudo AB in termino in input terminali extenso determinatur.
  
• Locutiones logicae scribi possunt per tabulam veritatis enumeratis.

(2) Digit expansionem numeralis comparator

• Connexio series, ad 8-bit, comparator numeralis expansus
  

• Connexio parallela, expansa ad 16-bit comparator numeralis.

• Cum parallelis connectuntur, celeritas est celeritas.
  

Articuli restrictiones pro magnitudine, videbis "[Notae Studiorum] 4. Circuitus logicae deductae (Part 2)" postea.